So I have found a Xilinx Spartan 3e starter kit board on sale for 25 euros, I currently have a tang nano 9k. Is it worth it? Is supported by some toolchain or is a museum piece?

I'm trying to add eye scan to a design that includes the Aurora 64B/66B IP Core on a Kintex 7. I've been trying to expose the eyescanreset and eyescantrigger ports from the transceiver, but any combination of settings of the core still ties those to '0' in the gtxe2_channel instantiation file. However, the eyescandataerror port is properly exposed outside of the IP Core.

Since this file is part of the IP Core, I'd have to unmanage it to be able to modify it, correct?

Out of curiosity, I did the same for a Kintex UltraScale, and the ports are correctly passed from the top of the example design all the way to the transceiver.

I guess this is yet another bug in the IP Core library? Or is there something I'm missing when it comes to the eye scan features in the Kintex 7 GTXs?

Vivado 2024.1 and 2025.2, by the way.

I have meet my supervisor and he said that i need to remove my memories module for now. He also said that I need to learn more about the load signal in my register module. How to use the load in my testbench? I know load was used to keep my register on and off. The thing is after I removed my memories module, it still the same. It still double accumulated.

My modules:

• Adder module:

module Adder #(

parameter WIDTH = 16, // total bits including integer and fraction

parameter FRAC = 10 // fractional bits (Q6.10 -> FRAC=10)

)(

input signed [WIDTH-1:0] a,

input signed [WIDTH-1:0] b,

output signed [WIDTH-1:0] sum

);

assign sum = a + b;

endmodule

• Multiplier module:

module Multiplier #(

parameter WIDTH = 16, // total bits including integer and fraction

parameter FRAC = 10 // fractional bits (Q6.10 -> FRAC=10)

)(

input signed [WIDTH-1:0] a,

input signed [WIDTH-1:0] b,

output signed [WIDTH-1:0] out

);

wire signed [2*WIDTH-1:0] out_full;

//full precision out size

assign out_full = a * b; // 16×16 → 32-bit signed

// Shift down from 20 fraction to 10 fraction

// Use arithmetic shift (>>>)

assign out = out_full >>> FRAC;

endmodule

• Register:

module Register #(

parameter WIDTH = 16, // total bits including integer and fraction

parameter FRAC = 10 // fractional bits (kept for interface consistency)

)(

input wire clk, // Clock signal

input wire rst_n, // Active-low synchronous reset

input wire load, // Load / Accumulate enable signal

input signed [WIDTH-1:0] d_in, // Data Input (WIDTH-bit fixed-point)

output reg signed [WIDTH-1:0] q_out // Accumulated Output

);

always @(posedge clk)

begin

if (!rst_n)

q_out <= {WIDTH{1'b0}}; // Dynamically sized zero reset

else if (load)

q_out <= q_out + d_in; // Accumulate only when load is high

// If load is 0, q_out automatically holds its value

end

endmodule

• MAC module:

module MAC#(

parameter WIDTH = 16,

parameter FRAC =3

)(

input wire clk,

input wire rst_n,

input wire load,

input wire signed [15:0] x_in,

input wire signed [15:0] w_in,

output wire signed [15:0] acc_out

);

wire signed [15:0] mul_out;

wire signed [15:0] add_out;

// 1. Multiplier Instance

Multiplier #(

.WIDTH(WIDTH),

.FRAC(FRAC)

) u_mult (

.a(x_in),

.b(w_in),

.out(mul_out)

);

// 2. Adder Instance (Kekal ada: darab + feedback acc_out)

Adder #(

.WIDTH(WIDTH),

.FRAC(FRAC)

)u_add (

.a(mul_out),

.b(acc_out),

.sum(add_out)

);

// 3. Register Instance (PIPO simpan hasil sum dari adder)

Register #(

.WIDTH(WIDTH),

.FRAC(FRAC)

)u_reg (

.clk(clk),

.rst_n(rst_n),

.load(load),

.d_in(add_out),

.q_out(acc_out)

);

endmodule

• test bench module:

module tb_MAC;

parameter WIDTH = 16;

parameter FRAC =10;

reg clk;

reg rst_n;

reg load;

reg signed [15:0] x_in;

reg signed [15:0] w_in;

wire signed [15:0] acc_out;

// Instantiate UUT

MAC#(

.WIDTH(WIDTH),

.FRAC(FRAC)

) uut (

.clk(clk),

.rst_n(rst_n),

.load(load),

.x_in(x_in),

.w_in(w_in),

.acc_out(acc_out)

);

// Clock Generation: 100 MHz (10 ns period)

always #5 clk = ~clk;

initial begin

// Initialize Signals

clk = 0;

rst_n = 0;

load = 0;

x_in = 16'sh0000;

w_in = 16'sh0000;

#100;

// Reset Pulse

rst_n = 1;

load=1;

x_in = 16'hFC2A; w_in = 16'hFD55; #10;

x_in = 16'hFC82; w_in = 16'hFBD0; #10;

x_in = 16'hFC30; w_in = 16'hFEDC; #10;

x_in = 16'hFC13; w_in = 16'hFB3B; #10;

x_in = 16'hFC14; w_in = 16'h047C; #10;

x_in = 16'hFC0E; w_in = 16'h08CE; #10;

x_in = 16'hFC1E; w_in = 16'h03B4; #10;

x_in = 16'hFC2D; w_in = 16'h01E8; #10;

// End the input

x_in = 16'h0000; w_in = 16'h0000;

#20;

$finish;

end

endmodule

Expected Value:
0.6396350860595703

1.553606033325195

1.825395584106445

2.995654106140136

1.896456718444824

-0.2746210098266604

-1.173279762268067

-1.628899574279786

Value in waveform:
0.638671875

2.1904296875

4.65234375

10.474609375

19.849609375

-26.47265625

10.1552734375

19.8544921875

-24.291015625

I’m using a bladeRF 2.0 micro A9 and recently I’ve been facing random FPGA loading issues.Sometimes the FPGA loads perfectly fine, but other times I get these errors:
dev->backend->load_fpga failed: File or device I/O failure
Failed to switch to NULL interface
The strange thing is that I’ve successfully loaded FPGA images multiple times using the same laptop and USB cable before. I’m using Windows 11. Could this be due to insufficient USB power from my laptop, or is there something else I should check?
I’m also considering programming through JTAG to see if that helps. Has anyone faced a similar issue?

Has anyone gotten an oa or heard back from Nvidia hardware intern roles? I applied and recently my application changed from “application submitted” to “in review “

If anyone has one collecting dust in their lab or office and is willing to part with it, please let me know your asking price and its current condition.

Please send me a PM with photos of the board if you have one available.
Thanks in advance!

Hello,

I am designing a programmable cartridge for MVS. I have selected the memories and microcontrollers, and I would like to include an FPGA per board in order to do the decoding, therefore, I am not in need of a very dense FPGA with lots of LUTs, but cheap, affordable and easy to work components. Programmation would be done through the microcontrollers, which would also be in charge of programming the memories.

Please, could you recommend a family or line with such characteristics?

Thank you very much in advance!

I'm working on a medical device safety controller on an Artix-7. Nothing too complicated, but the development process is mostly new to me.

One of the real joys I've found is seeing the vast number of warnings that Vivado dumps out. Almost all of them seem meaningless, but as this is a medical device, I want to do my due diligence to make sure I review them as best I can. I'd also like to leave a note, initials, and date on each one as I check them off. This last bit doesn't seem to be well supported.

I've been using Claude to help me through this, and it came up with a python script that I can run after synthesis and implementation. It parses runme.log and generates a csv file where I can add all this information. If I rerun systhesis and implementation and then this script, it will check for changes and mark warnings as new, reviewed, or not seen. It also created a separate tcl script to suppress some of the spamier messages that come from Vivado IP blocks. There are some other bells and whistles too.

My question is this: Is this a good process or an AI fever dream? How do other people approach this problem?

Hello guys, I just started my electronic engineering course at uni and was looking into different things I can do. I kind of got interested in career in semiconductors or robotics fields. I was wondering if it is realistic to start practicing with FPGA boards as first year, since a lot of people that I see in this community started FPGA boards as 3rd year cs students or engineering postgraduates. Also, could you give me some project ideas I could use for the uni fund application. Appreciate all the input, including personal stories, resources, advice etc. :)

I'm building a neuron accumulator using Fixed-point Q6.10 via Vivado for my final year project (This project was given to me even though i don't like digital electronics that much but I still need to do it). The pic i've clipped is the block diagram for it. That's for non bias and activation function, bias and activation function will be added after i've completed this one first. The thing is my neuron accumulator accumulated twice each address, maybe because of the RAM running 2 clocks per address but I still need to put it.

I've made the modules for adder, multiplier, register and memory. I need help for how to fix this top level module so that it won't accumulate twice in one load after it changes address and how to do it.

here is my email: hafizairi10@gmail.com if anyone will be giving me a hand. please help me, i'm begging😭🙏🏼.

Prompted by this recent thread that described a test bench failure caused by a simulated clock not being exactly the right frequency, I thought I'd post a solution for generating test clocks with zero frequency error.

This is not a replacement for the usual clk <= not clk after 5 ns; or clk <= #5 !clk; as these are fine for most use cases and likely more efficient than the method described here.
Instead, this clock generator is meant for things like making two clocks that have an accurate 200 ppm frequency difference for testing clock domain crossers in Ethernet interfaces in simulation, etc.

This is based on a component that I've been using in testbenches for well over 20 years. It's been tested in many different simulators.

I'm presenting a very cut down version to explain the technique. The full version that I use in testbenches (that I'm not posting!) has extra features such as: an enable input, true and inverted outputs (for driving differential inputs), divided outputs, all outputs update in the same delta cycle, settable initial values, a control voltage input (with settable Kv and modulation bw) to simulate VCXOs, etc.

The VHDL version measures the simulator timing resolution. All edges of the output clock are aligned with integer multiples of that time. The Verilog version uses a fixed timing resolution (which may or may not suit any particular frequency).

There will be some jitter on the generated clock as a consequence of the way the output edges are aligned (unless the (half) period is an exact multiple of the timing resolution, of course).

I’m looking to take on freelance work in FPGA, Verilog, embedded, and SoC design. For those of you who freelance or have done so in the past, how do you find opportunities, and how do you approach the right person (the decision-maker) at a company to start a conversation?

Any advice on platforms, networking, or how you got your first clients would be appreciated. Thanks!

Vivado reported timing met on my design, but it still had two unsynchronized clock crossings. So I built FPGA Project Analyzer skill for it:

https://github.com/al-nafisah/fpga-project-analyzer

Point it at a Vivado, Zynq or PYNQ project folder and it gives you a clickable diagram of the design, from block design down to RTL, with wires coloured by clock domain. It also flags unsynchronized clock crossings, missing pin constraints, and common reset, address-map and PYNQ mistakes.

Hi all,

I would love to hear your experience of using AI in RTL coding and building complete projects, what was your experience in writing RTL codes, building full projects from scratch, debugging and achieving timing closure.
Have you tried AMD ross? What do you think about it?

Je me suis amusé avec Claude ce week-end. Ça tourne bien sur FPGA même si pour l'instant c'est plus agréable de lancer une partie de SOR2. Je vais faire des itérations jusqu'à avoir un jeu vraiment sympa.

DigSim: a digital logic simulator in Python that you can also feed Verilog

Hi! DigSim is a logic simulator you can play around with. You drag switches, push buttons, gates, flip-flops, LEDs and 7-segment displays onto a canvas, wire them up, and watch the circuit run live.

Processing img 5azlufgu0nxh1...

Some things it can do:

- Verilog as components. Write a module in the built-in editor, press Ctrl+B, and it becomes a part you can wire up. Yosys does the synthesis and comes bundled, so there's nothing else to install. Modules with parameters work too, so one counter file can give you a 4-bit and a 16-bit copy.

- See what's going on. There's a logic analyzer component, a buzzer, and VCD output you can open in GTKWave.

- Script it from Python. Build circuits in code and write pytest testbenches for your Verilog. One of the examples runs a 6502 CPU.

- It runs on Linux, Windows and macOS.

If you want to try it: pip install digsim-logic-simulator, then python -m digsim.app.
If you use uv, uvx digsim-logic-simulator works too.

- GitHub: https://github.com/freand76/digsim

- Docs, with a getting-started tutorial: https://freand76.github.io/digsim/

It's a hobby project, so it has rough edges. I'd love to hear what you think, what breaks, or what you'd like it to do!

I found job after one year. I was not doing any work for an entire year.

When I was laid off there was no ai. But it is everywhere now. I don’t know how it is used in our industry. I am very nervous and worried I won’t be able to catch up or cope. I will be the dinosaur in the team.

I have only used ai as a substitute for google.

If you work in fpga development field in corporate setting -
could you please share how you use ai in your daily work.
Are there any ai skills I can pick up in a week or so before I start ?

Thank you

So as the title suggests, i got a job interview for a research assistant position at NUS, they are working on quantum computers based on trapped ions. And they are putting together a team of electronics engineers to control the ion trap quantum processor.

They want somebody who has practical exp in one of these- digital logic design in VHDL/Verilog, DSP and RF electronics. I only know the first, with well documented beginner to intermediate level projects in GitHub. Since, i got the email i've been studying quantum computers but its way too advanced for me in such a limited amount of time.

Now I am a fresh masters grad with no industry experience and i don't know anything about research positions at universities. What are they like? and what kind of interview can I expect? This will be my first interview ever, any tips will be greatly appreciated.

Thanks.

I am at my final year , had a good experience , collected some great projects (rv32ima , hardware accelerated ai on an fpga , fpga based test jig , ... ) and while looking for my first job i was hit with a realization : all companies looking to hire entry level are either defense contractors or dual-use technologies (microchips included) , both i want to run from like the plague ( ethical resons )
so ... are there any other sectors with demand for entry fpga engineers ?

Hello ,

I ´m using the FPGA loader inside of MSYS UCRT64 to flash the nanomig and the kick roms on the Sipeed Tang Nano 20K
But i´m getting this errors , can anybody help me?

Hello,

I just finished reading a book called efficient processing of deep neural networks and I thought I would apply it to reality. It is about creating a hardware AI accelerator from scratch, which is definitely a very relevant topic in today's world.
I was looking for people who are interested on working on it together, share thoughts and perspectives and learn from each other.
I started applying it on an open source RISC V processor called picorv32.
You can find my github repo here:

https://github.com/Xynorax/picorv32/tree/ai_acc

So to begin with i am not a professional verilog programmer, it is more like a hobby/interest of mine. By career i am an EE engineer and often i design HW with FPGA SOC etc so i am approaching this choose mostly from that side of the problem. (mostly PCB difficulty and part availability )

I want to make a few boards to play with a few ideas for personal use and i looked up FPGA prices for what i know already and more or less have a good idea is good enough ( probably resource overkill if like i said in my case i am happy if it works but how small i get the desing).

Anyway i noticed Series 6 were way cheaper then series 7 and since i dont need the greatest stuff i was considering series 6 BUT that use something called ISE for development and series 7 use s vivado.

Choices choices i have no idea IF it is worth using ISE now or simply use the more expensive series 7.

In terms of PCB it is more or less same difficulty, what concerns me is the SW licencing and community support. Since it is for personal use i want something free or cheap since it is long term projects since i do it all. Also are series 6 so old that people dont remember how to debug them ?

Anyway here is what i am considering making:

-1 ETH 100M maybe if i am very ambitious ( on the fpga verilog side) 1G

- 1-2 USB mostly to play with some FTDI chip tho i can also do that with a dev board and wires so not sure if it is going to happen

- VGA dac made from IO and resistors MCU can do it so should be doable

- SMPS control YES i know it is overkill but often i cant get MCU timers to behave like i want them to. but this is mostly IO that i can also make use of some io from a dev board

- use IO to emulate some older interface

So what is your opinion ? series 6 or 7?

Also is this simple enough to get a dev board and maybe a small custom board and use the PMOD connectors? ( for this case also series 6 or 7? )

Hi guys, I'm curious if anyone here has experience running a service business in chip design / Fpga or EDA. I'm trying to figure out what skills are worth learning if I want to sell services to companies in this industry, either as a freelancer or by building a small business around a specific service. I've heard that it is very much about trust and connections, so I'm wondering how realistic it is to get started without an existing network. Could you start on Upwork, build a portfolio, and use LinkedIn/email/? to find clients, or is that not really how things work.

For those of you who have done this, I'd love to know:

What services have you actually sold, and who were your clients?

What skills would you focus on learning if you were starting today?

Are there things semiconductor startups commonly outsource instead of hiring someone full-time?

How did you get your first clients?

Honestly, is this worth pursuing, or is it too difficult to break into without connections?

Thanks a lot!